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19-1467; Rev 1; 12/99
+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery
General Description
The MAX3880 deserializer with clock recovery is ideal for converting 2.488Gbps serial data to 16-bit-wide, 155Mbps parallel data for SDH/SONET applications. Operating from a single +3.3V supply, this device accepts high-speed serial-data inputs and delivers lowvoltage differential-signal (LVDS) parallel clock and data outputs for interfacing with digital circuitry. The MAX3880 includes a low-power clock recovery and data retiming function for 2.488Gbps applications. The fully integrated phase-locked loop (PLL) recovers a synchronous clock signal from the serial NRZ data input; the signal is then retimed by the recovered clock. The MAX3880's jitter performance exceeds all SDH/SONET specifications. An additional 2.488Gbps serial input is available for system loopback diagnostic testing. The device also includes a TTL-compatible loss-of-lock (LOL) monitor and LVDS synchronization inputs that enable data realignment and reframing. The MAX3880 is available in the extended temperature range (-40C to +85C) in a 64-pin TQFP-EP (exposed pad) package. o Single +3.3V Supply o 910mW Operating Power o Fully Integrated Clock Recovery and Data Retiming o Exceeds ANSI, ITU, and Bellcore Specifications o Additional High-Speed Input Facilitates System Loopback Diagnostic Testing o 2.488Gbps Serial to 155Mbps Parallel Conversion o LVDS Data Outputs and Synchronization Inputs o Tolerates >2000 Consecutive Identical Digits o Loss-of-Lock Indicator
Features
MAX3880
Ordering Information
PART MAX3880ECB *Exposed pad Pin Configuration appears at end of data sheet. TEMP. RANGE -40C to +85C PIN-PACKAGE 64 TQFP-EP*
Applications
2.488Gbps SDH/SONET Transmission Systems Add/Drop Multiplexers Digital Cross-Connects
Typical Application Circuit
+3.3V 0.01F +3.3V VCC FIL IN+ OUT+ SDI+ PD0+ PD15-
PHADJ+
PHADJ-
VCC
PD15+ 100*
VCC
MAX3866
PRE/POSTAMPLIFIER OUTLOP SDI-
MAX3880
PD0PCLK+ SLBI-
100*
OVERHEAD TERMINATION
100* PCLKSYNC+
TTL
SLBI+
SIS SYSTEM LOOPBACK
FIL+
FIL-
GND
LOL SYNC-
CF 1F TTL TTL *REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION. THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50.
________________________________________________________________ Maxim Integrated Products
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+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery MAX3880
ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage (VCC)...............................-0.5V to +7.0V Input Voltage Level (SDI+, SDI-, SLBI+, SLBI-, SYNC+, SYNC-)........................... (VCC - 0.5V) to (VCC + 0.5V) Input Current Level (SDI+, SDI-, SLBI+, SLBI-)................10mA Voltage at LOL, SIS, PHADJ+, PHADJ-, FIL+, FIL- .................................................-0.5V to (VCC + 0.5V) Output Current LVDS Outputs ............................................10mA Continuous Power Dissipation (TA = +85C) TQFP (derate 33.3mW/C above +85C) .......................1.44W Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-55C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, differential loads = 100 1%, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) PARAMETER Supply Current Differential Input Voltage Single-Ended Input Voltage Input Termination to Vcc Input Voltage Range Differential Input Threshold Threshold Hysteresis Differential Input Resistance Output High Voltage Output Low Voltage Differential Output Voltage Change in Magnitude of Differential Output Voltage for Complementary States Output Offset Voltage Change in Magnitude of Output Offset Voltage for Complementary States Single-Ended Output Resistance Change in Magnitude of SingleEnded Output Resistance for Complementary Outputs Input High Voltage Input Low Voltage Input Current Output High Voltage Output Low Voltage 2 VOH VOL SYMBOL ICC VID VIS RIN VI VIDTH VHYST RIN VOH VOL 0.925 Figure 2 250 400 25 1.125 1.275 25 85 Differential input voltage = 100mV Common-mode voltage = 50mV 0 -100 78 100 115 1.475 Figure 1 50 VCC - 0.4 50 2.4 100 CONDITIONS MIN TYP 275 MAX 380 800 VCC + 0.2 UNITS mA mVp-p V V mV mV V V mV mV V mV
SERIAL DATA INPUTS (SDI, SLBI)
LVDS INPUTS AND OUTPUTS (SYNC, PCLK, PD_)
|VOD| |VOD|
VOS
VOS
RO 40 95
140
RO
2.5
10
%
TTL INPUTS AND OUTPUTS (SIS, LOL) VIH VIL -10 2.4 2.0 0.8 +10 VCC 0.4 V V A V V
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+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, differential loads = 100 1%, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) (Note 1) PARAMETER Serial Data Rate Parallel Output Data Rate Parallel Clock-to-Data Output Delay tCLK-Q Figure 5 f = 70kHz (Note 2) Jitter Tolerance f = 100kHz f = 1MHz f = 10MHz Tolerated Consecutive Identical Digits Input Return Loss (SDI, SLBI) 100kHz to 2.5GHz 2.5GHz to 4.0GHz 200 2.31 1.74 0.38 0.28 SYMBOL SDI CONDITIONS MIN TYP 2.488 155.52 450 3.3 2.41 0.57 0.46 >2,000 -18 -11 Bits dB UIp-p 900 MAX UNITS Gbps Mbps ps
MAX3880
Note 1: AC characteristics are guaranteed by design and characterization. Note 2: At jitter frequencies <70kHz, the jitter tolerance characteristics exceed the ITU/Bellcore specifications. The low-frequency jitter tolerance outperforms the instrument's measurement capability.
SDI+ SDI-
25mV MIN 400mV MAX
(SDI+) - (SDI-)
VID
50mVp-p MIN 800mVp-p MAX
Figure 1. Input Amplitude
PD+ D PDVPDSINGLE-ENDED OUTPUT VPD+ VOH RL = 100 V VOD
|VOD|
VOS VOL
VPD+ - VPDDIFFERENTIAL OUTPUT 0V (DIFF) 0V
+VOD VOD, p-p = VPD+ - VPD-VOD
Figure 2. Driver Output Levels _______________________________________________________________________________________ 3
+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery MAX3880
Typical Operating Characteristics
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
RECOVERED DATA AND CLOCK (DIFFERENTIAL OUTPUT)
MAX3880-01
SUPPLY CURRENT vs. TEMPERATURE
MAX3880-02
JITTER TOLERANCE
MAX3880-03
300 290 SUPPLY CURRENT (mA) 280 270 VCC = 3.0V 260 250 240 VCC = 3.6V
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DATA
223 - 1 PATTERN
INPUT JITTER (UIPp-p) 75 100
1
CLOCK
0.1 -50 -25 0 25 50 10 100 1,000 10,000 TEMPERATURE (C) JITTER FREQUENCY (kHz)
1.64ns/div
JITTER TOLERANCE vs. INPUT VOLTAGE
MAX3880-04
BIT ERROR RATE vs. INPUT VOLTAGE
PCLK TO DATA OUTPUT PROPAGATION DELAY (ps)
MAX3880-05
PARALLEL CLOCK TO DATA OUTPUT PROPAGATION DELAY vs. TEMPERATURE
MAX3880-06
0.8 0.7 JITTER TOLERANCE (UIp-p) 0.6 0.5 0.4 0.3 0.2 0.1 0 10 100 INPUT VOLTAGE (mVp-p) SONET SPEC JITTER FREQUENCY = 5MHz JITTER FREQUENCY = 1MHz
10-3 10-4 10-5 BIT ERROR RATE 10-6 10-7 10-8 10-9 10-10
700
600
500
400
300
200 -50 -25 0 25 50 75 100 TEMPERATURE (C)
1,000
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5 10.0
INPUT VOLTAGE (mVp-p)
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+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery
Pin Description
PIN 1, 17, 25, 33, 41, 49, 56, 62, 64 2 3 4, 7, 10, 13, 24, 32, 40, 48, 57 5 6 8 9 11 12 14 15 16 18 19 20, 22, 26, 28, 30, 34, 36, 38, 42, 44, 46, 50, 52, 54, 58, 60 21, 23, 27, 29, 31, 35, 37, 39, 43, 45, 47, 51, 53, 55, 59, 61 63 EP NAME GND FIL+ FILVCC Ground Positive Filter Input. PLL loop filter connection. Connect a 1.0F capacitor between FIL+ and FIL-. Negative Filter Input. PLL loop filter connection. Connect a 1.0F capacitor between FIL+ and FIL-. +3.3V Supply Voltage Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not used. Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not used. Positive Serial Data Input. 2.488Gbps data stream. Negative Serial Data Input. 2.488Gbps data stream. Positive System Loopback Input. 2.488Gbps data stream. Negative System Loopback Input. 2.488Gbps data stream. Signal Input Selection. TTL low for normal data input (SDI). TTL high for system loopback input (SLBI). Negative Synchronizing Pulse LVDS Input. Pulse the SYNC signal high for at least four serial-data bit periods (1.6ns) to shift the data alignment by dropping 1 bit. Positive Synchronizing Pulse LVDS Input. Pulse the SYNC signal high for at least four serial-data bit periods (1.6ns) to shift the data alignment by dropping 1 bit. Negative Parallel Clock LVDS Output Positive Parallel Clock LVDS Output FUNCTION
MAX3880
PHADJ+ PHADJSDI+ SDISLBI+ SLBISIS SYNCSYNC+ PCLKPCLK+
PD0- to PD15-
Negative Parallel Data LVDS Outputs. Data is updated on the negative transition of the PCLK signal (Figure 5).
PD0+ to PD15+
Positive Parallel Data LVDS Outputs. Data is updated on the negative transition of the PCLK signal (Figure 5).
LOL Exposed Pad
Loss-of-Lock Output. PLL loss-of-lock monitor, TTL active low (internal 10k pull-up resistor). The LOL monitor is valid only when a data stream is present on the inputs to the MAX3880. Ground. This must be soldered to a circuit board for proper thermal performance (see Package Information).
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+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery MAX3880
PHADJ+ VCC PHADJFIL+ FIL-
50 SDI+ AMP SDID CK Q LVDS PD15PD15+
MUX SLBI+ AMP SLBI-
PHASE & FREQUENCY DETECTOR
LOOP FILTER
VCO
16-BIT DEMULTIPLEXER PD1+ LVDS PD1-
50 PD0+ LVDS PD0VCC SIS SYNC100 SYNC+ LVDS
MAX3880
CLOCK DIVIDER LVDS
PCLK+ PCLK-
TTL
LOL
Figure 3. MAX3880 Functional Diagram
Detailed Description
The MAX3880 deserializer with clock recovery converts 2.488Gbps serial data to 16-bit-wide, 155Mbps parallel data. The device combines a fully integrated phaselocked loop (PLL), input amplifier, data retiming block, 16-bit demultiplexer, clock divider, and LVDS output buffer (Figure 3). The PLL consists of a phase/frequency detector (PFD), a loop filter, and a voltage-controlled oscillator (VCO). The MAX3880 is designed to deliver the best combination of jitter performance and power
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dissipation by using a fully differential signal architecture and low-noise design techniques. The PLL recovers the serial clock from the serial input data stream. The demultiplexer generates a 16-bit-wide 155Mbps parallel data output. The synchronization inputs (SYNC+, SYNC-) realign the output data word. Realignment is guaranteed to occur within two complete PCLK cycles of the SYNC signal's positive transition. During synchronization, the first incoming bit of data during that PCLK cycle is
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+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery
dropped, shifting the alignment between PCLK and data by 1 bit. The SYNC signal must be at least four serial bit periods wide (4 x 402ps). See Figure 4 for the timing diagram and Figure 5 for the timing parameters diagram. clock is derived by sampling the in-phase and quadrature VCO outputs on both edges of the data input signal. Depending on the polarity of the frequency difference, the FD drives the VCO until the frequency difference is reduced to zero. Once frequency acquisition is complete, the FD returns to a neutral state. False locking is completely eliminated by this digital frequency detector.
MAX3880
Input Amplifier
The input amplifiers on both the main data and system loopback accept a differential input amplitude from 50mVp-p to 800mVp-p. The bit error rate (BER) is better than 1 x 10-10 for input signals as small as 9.5mVpp, although the jitter tolerance performance will be degraded. For interfacing with PECL signal levels, see Applications Information.
Loop Filter and VCO
The phase detector and frequency detector outputs are summed into the loop filter. A 1.0F capacitor, CF, is required to set the PLL damping ratio. The loop filter output controls the on-chip LC VCO running at 2.488GHz. The VCO provides low phase noise and is trimmed to the correct frequency.
Phase Detector
The phase detector in the MAX3880 produces a voltage proportional to the phase difference between the incoming data and the internal clock. Because of its feedback nature, the PLL drives the error voltage to zero, aligning the recovered clock to the center of the incoming data eye for retiming. The external phase adjust pins (PHADJ+, PHADJ-) allow the user to vary the internal phase alignment.
Loss-of-Lock Monitor
A loss-of-lock (LOL) monitor is included in the MAX3880 frequency detector. A loss-of-lock condition is signaled immediately with a TTL low. When the PLL is frequency-locked, LOL switches to TTL high in approximately 800ns. Note that the LOL monitor is only valid when a data stream is present on the inputs to the MAX3880. As a result, LOL does not detect a loss-of-power condition resulting from a loss of the incoming signal.
Frequency Detector
The digital frequency detector (FD) aids frequency acquisition during start-up conditions. The frequency difference between the received data and the VCO
D15
D14
D13
SDI SYNC
PCLK
(LSB) PD0
D0
D16
D32
D48
D65
PD1 * * * (MSB) PD15 TRANSMITTED FIRST
D1
D17
D33
D49 1 BIT HAS SLIPPED IN THIS TIME SLICE
D66
D15
D31
D47
D64
D80
Figure 4. Timing Diagram _______________________________________________________________________________________ 7
+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery MAX3880
PCLK tCLK-Q PD0-PD15 3.3V
MAX3880
PHADJ+ (PIN 5)
NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCLK = (PCLK+) - (PCLK-). PHADJ- (PIN 6)
Figure 5. Timing Parameters
Low-Voltage Differential-Signal (LVDS) Inputs and Outputs
The MAX3880 features LVDS inputs and outputs for interfacing with high-speed digital circuitry. The LVDS standard is based on the IEEE 1596.3 LVDS specification. This technology uses 500mVp-p to 800mVp-p differential low-voltage swings to achieve fast transition times, minimize power dissipation, and improve noise immunity. For proper operation, the parallel clock and data LVDS outputs (PCLK+, PCLK-, PD_+, PD_-) require 100 differential DC termination between the positive and negative outputs. Do not terminate these outputs to ground. The synchronization LVDS inputs (SYNC+, SYNC-) are internally terminated with 100 differential input resistance and therefore do not require external termination.
Figure 6. Phase-Adjust Resistor-Divider
Applications Information
Consecutive Identical Digits (CIDs)
The MAX3880 has a low phase and frequency drift in the absence of data transitions. As a result, long runs of consecutive zeros and ones can be tolerated while maintaining a BER of 1 x 10-10. The CID tolerance is tested using a 2 13 - 1 pseudorandom bit stream (PRBS), substituting a long run of zeros to simulate the worst case. A CID tolerance of greater than 2,000 bits is typical.
Phase Adjust
The internal clock is aligned to the center of the data eye. For specific applications, this sampling position can be shifted using the PHADJ inputs to optimize BER performance. The PHADJ inputs operate with differential input voltages up to 1.5V. A simple resistor-divider with a bypass capacitor is sufficient to set these levels (Figure 6). When the PHADJ inputs are not used, they should be tied directly to VCC.
Design Procedure
Jitter Tolerance and Input Sensitivity Trade-Offs
When the received data amplitude is higher than 50mVp-p, the MAX3880 provides a typical jitter tolerance of 0.46 UI at jitter frequencies greater than 10MHz. The SDH/SONET jitter tolerance specification is 0.15UI, leaving a jitter allowance of 0.31UI for receiver preamplifier and postamplifier design. The BER is better than 1 x 10 -10 for input signals greater than 9.5mVp-p. At 25mVp-p, jitter tolerance will be degraded, but will still be above the SDH/SONET requirement. Trade-offs can be made between jitter tolerance and input sensitivity according to the specific application. See the Typical Operating Characteristics for Jitter Tolerance and BER vs. Input Voltage graphs.
System Loopback
The MAX3880 is designed to allow system loopback testing. The user can connect a serializer output (MAX3890) in a transceiver directly to the SLBI+ and SLBI- inputs of the MAX3880 for system diagnostics. To select the SLBI inputs, apply a TTL logic high to the SIS pin.
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+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery
Interfacing with PECL Input Levels
When interfacing with differential PECL input levels, it is important to attenuate the signal while still maintaining 50 termination (Figure 7). AC-coupling is also required to maintain the input common-mode level.
VCC
MAX3880
Layout Techniques
For best performance, use good high-frequency layout techniques. Filter voltage supplies, keep ground connections short, and use multiple vias where possible. Use controlled impedance transmission lines to interface with the MAX3880 high-speed inputs and outputs. Power-supply decoupling should be placed as close to VCC as possible. To reduce feedthrough, take care to isolate the input signals from the output signals.
50 0.1F PECL LEVELS 0.1F SDI25 50
SDI+
100
25
Chip Information
TRANSISTOR COUNT: 4102
MAX3880
Figure 7. Interfacing with PECL Input Levels
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+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery MAX3880
Pin Configuration
PD15+
PD14+
PD13+
PD12+
PD11+
PD15-
PD14-
PD13-
PD12-
PD11-
GND
GND
GND
64
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
GND FIL+ FILVCC PHADJ+ PHADJVCC SDI+ SDIVCC SLBI+ SLBIVCC SIS SYNCSYNC+
VCC
TOP VIEW
GND
LOL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
48 47 46 45 44 43 42 41
VCC PD10+ PD10PD9+ PD9PD8+ PD8GND VCC PD7+ PD7PD6+ PD6PD5+ PD5GND
MAX3880
40 39 38 37 36 35 34 33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PD3-
PD2+
PD4-
PD1+
PD4+
GND
VCC
PD2-
PCLK-
PCLK+
PD0+
TQFP-EP
10
______________________________________________________________________________________
PD3+
PD0-
PD1-
GND
VCC
+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery
Package Information
64L, TQFP.EPS ______________________________________________________________________________________ 11
MAX3880
+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery MAX3880
Package Information (continued)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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